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Sun Fire X4600 & Sun Fire X4600 M2 BIOS Post Codes

  • 03 - Disable NMI, Parity, video for EGA, and DMA controllers. At this point, only ROM accesses are to the GPNV. If BB size is 64K, require to turn on ROM Decode below FFFF0000h. It should allow USB to run in E000 segment. The HT must program the NB specific initialization and OEM specific initialization can program if it need at beginning of BIOS POST, like overriding the default values of Kernel Variables.
  • 04 - Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.
  • 05 - Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
  • 06 - Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POSTINT1ChHandlerBlock.
  • C0 - Early CPU Init Start--Disable Cache--Init Local APIC.
  • C1 - Set up boot strap processor information.
  • C2 - Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
  • C3 - Errata workarounds applied to the BSP (#78 and #110).
  • C5 - Enumerate and set up application processors. This includes microcode loading and workarounds for errata (#78, #110, #106, #107, #69, #63).
  • C6 - Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state.
  • C7 - The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.
  • 0A - Initializes the 8042 compatible Keyboard Controller.
  • 0B - Detects the presence of PS/2 mouse.
  • 0C - Detects the presence of Keyboard in KBC port.
  • 0E - Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Decompress all available language, BIOS logo, and Silent logo modules.
  • 13 - Initialize PM regs and PM PCI regs at Early-POST. Initialize multi host bridge, if system support it. Setup ECC options before memory clearing. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory. Enable PCI-X clock lines in the 8131.
  • 20 - Relocate all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If less than 5 CPU sockets are present on a board, subsequent CPUs entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present, entry points are separated by 200h bytes. CPU module will be responsible for the relocation of the CPU to correct address. NOTE: APs are left in the INIT state.
  • 24 - Decompress and initialize any platform specific BIOS modules.
  • 30 - Initialize System Management Interrupt.
  • 2A - Initializes different devices through DIM.
  • 2C - Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
  • 2E - Initializes all the output devices.
  • 31 - Allocate memory for ADM module and decompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
  • 33 - Initializes the silent boot module. Set the window for displaying text information.
  • 37 - Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
  • 38 - Initializes different devices through DIM.
  • 39 - Initializes DMAC-1 and DMAC-2.
  • 3A - Initialize RTC date/time.
  • 3B - Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
  • 3C - By this point, RAM read/write test is completed, program memory holes or handle any adjustments needed in RAM size with respect to NB. Test if HT Module found an error in Boot Block and CPU compatibility for MP environment.
  • 40 - Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.
  • 50 - Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
  • 52 - Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
  • 60 - Initializes NUM-LOCK status and programs the KBD typematic rate.
  • 75 - Initialize Int-13 and prepare for IPL detection.
  • 78 - Initializes IPL devices controlled by BIOS and option ROMs.
  • 7A - Initializes remaining option ROMs.
  • 7C - Generate and write contents of ESCD in NVRam.
  • 84 - Log errors encountered during POST.
  • 85 - Display errors to the user and gets the user response for error.
  • 87 - Execute BIOS setup if needed/requested.
  • 8C - After all device initialization is done, programmed any user selectable parameters relating to NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node. Workaround for erratum #101 applied here.
  • 8D - Build ACPI tables (if ACPI is supported).
  • 8E - Program the peripheral parameters. Enable/Disable NMI as selected.
  • 90 - Late POST initialization of system management interrupt.
  • A0 - Check boot password if installed.
  • A1 - Clean-up work needed before booting to OS.
  • A2 - Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
  • A4 - Initialize runtime language module.
  • A7 - Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs.
  • A8 - Prepare CPU for OS boot including final MTRR values.
  • A9 - Wait for user input at config display if needed.
  • AA - Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
  • AB - Prepare BBS for Int 19 boot.
  • AC - Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.
  • B1 - Save system context for ACPI.
  • 00 - Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLIHLT state.
  • 61 to 70 - OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next.
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